Multiple Projects Upgraded to newest toolchain (end of 2020)

The following eight FPGA example projects were originally designed with Vivado/SDK 2019.1 or Vivado/Vitis 2020.1. They have now been upgraded to each work with Vivado/Vitis 2020.2 . As Vitis is a newer IDE released by Xilinx a year ago, piecing together a Vitis project is somewhat different than was the previous SDK IDE. For these examples, Vivado 2020.2 is used to synthesize the design to a Xilinx FPGA .bit bitstream. This is the only tool flow for the pure HDL designs. For Microblaze and Zynq designs: after this, Vivado is used to export a .xsa archive containing bitstream and hardware export. Two options follow. Either a new Vitis project can be created in a new Vitis Workspace; and the sources from the git checkout folder Vitis-Sources can be copied to the src/ folder of the Vitis Application. Or, a Vitis project archive vitis_export_archive.ide.zip from Vitis-Archives can be imported into an empty Vitis Workspace. It is worthy of note that the GNU Make makefiles contained under the IP folder can sometimes exhibit different behavior on Windows 10 Pro versus Ubuntu Linux. Recognizing this, and the possibility of other cross-platform differences, the Vitis-Archives folder contains a ZIP project import each for Ubuntu and for Windows, each tested to compile and execute successfully with the respective desktop onto the target hardware.

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Update of FPGA example projects to 2020 toolchain.

Multiple Projects Upgraded to newest toolchain (end of 2020)

fpga-serial-acl-tester-1

fpga-serial-acl-tester-2

fpga-serial-mem-tester-1

fpga-serial-mem-tester-2

fpga-colors-tester-1

fpga-colors-tester-2

fpga-iic-hygro-tester-1

fpga-iic-hygro-tester-2