fpga-serial-acl-tester-1

FPGA Serial ACL Tester Version 1 by Timothy Stotts

FPGA Serial ACL Tester Version 1 project and source code

Description

A small FPGA project of different implementations for testing Measurement and Activity Events of a SPI accelerometer. The design targets the Digilent Inc. Arty-A7-100T FPGA development board containing a Xilinx Artix-7 FPGA. Three peripherals are used: Digilent Inc. Pmod ACL2, Digilent Inc. Pmod CLS., Digilent Inc. Pmod SSD.

The design is broken into three groupings.

The folder ACL-Tester-Design-AXI contains a Xilinx Vivado IP Integrator plus Xilinx SDK design. A microblaze soft CPU is instantiated to talk with board components, an accelerometer peripheral, a 16x2 character LCD peripheral and a two-digit Seven Segment Display. A Xilinx SDK project contains a very small FreeRTOS program in C; drivers for the peripherals, a real-time task to operate and poll the accelerometer, two real-time tasks to display data, and a real-time task to color-mix RGB LEDs.

The folder ACL-Tester-Design-Single-Clock-Verilog contains a Xilinx Vivado project with sources containing only Verilog-2001 modules. Plain HDL without a soft CPU or C code is authored to talk with board components, an accelerometer peripheral, a 16x2 character LCD peripheral and a two-digit Seven Segment Display. The project is named “Single Clock” as clock enable pulses are used instead of clock dividers as much as possible throughout the design.

The folder ACL-Tester-Design-Single-Clock-VHDL contains a Xilinx Vivado project with sources containing only VHDL-2002 and VHDL-2008 modules. Plain HDL without a soft CPU or C code is authored to talk with board components, an accelerometer peripheral, a 16x2 character LCD peripheral and a two-digit Seven Segment Display. The project is named “Single Clock” as clock enable pulses are used instead of clock dividers as much as possible throughout the design.

These three groupings of design provide equivalent functionality, excepting that the HDL designs provide additional animation effect of the board’s three-emitter RGB LEDs. Additionally, work is merged from the feature/ssd_with_presets branch to add a single Pmod SSD to the Pmod Jack A for the purpose of displaying the button-selection of one of ten ADXL362 configuration preset values for each of Activity Detection threshold/timer and Inactivity Detection threshold/timer. All three groupings are complete for this feature, but are not yet release ready. Checkouts for the design without a Pmod SSD peripheral should refer to release tag Serial_ACL_Tester_Release_A . Checkouts for the latest experimental implementation of adding Pmod SSD to Pmod Jack JA and using Buttons 0 and 1 to select threshold/timer presets, should refer to tag Serial_ACL_Tester_HDL_Prerelease_6B or the HEAD of the master branch.

Naming conventions notice

The Pmod peripherals used in this project connect via a standard bus technology design called SPI. The use of MOSI/MISO terminology is considered obsolete. COPI/CIPO is now used. The MOSI signal on a controller can be replaced with the title ‘COPI’. Master and Slave terms are now Controller and Peripheral. Additional information can be found here. The choice to use COPI and CIPO instead of SDO and SDI for single-direction bus signals is simple. On a single peripheral bus with two data lines of fixed direction, the usage of the signal name “SDO” is dependent on whether the Controller or the Peripheral is the chip being discussed; whereas COPI gives the exact direction regardless of which chip is being discussed. The author of this website agrees with the open source community that the removal of offensive language from standard terminology in engineering is a priority.

Project homepage

FPGA Serial ACL Tester Version 1 project and source code

Project information document:

Serial ACL Readings Tester info

Diagrams design document:

Serial ACL Design Diagrams info

Target device assembly: Arty-A7-100T with Pmod ACL2, Pmod CLS, Pmod SSD, on extension cables

Target device assembly

Block diagram architecture of the HDL designs of fpga-serial-acl-tester-1:

ACL Tester Architecture Diagram

Top Port diagram architecture of the HDL designs:

ACL Tester Top Ports Diagram