fpga-serial-acl-tester-1

Mixed-language Verification with Riviera-PRO

FPGA Serial ACL Tester Version 1 by Timothy Stotts

FPGA Serial ACL Tester Version 1 project and source code

Previous project posting on GitHub.io site

Description

A small FPGA project of different implementations for testing Measurement and Activity Events of a SPI accelerometer. The design targets the Digilent Inc. Arty-A7-100T FPGA development board containing a Xilinx Artix-7 FPGA. Three peripherals are used: Digilent Inc. Pmod ACL2, Digilent Inc. Pmod CLS., Digilent Inc. Pmod SSD.

The design is broken into three groupings: Xilinx AXI subsystem, Verilog-Only RTL, VHDL-Only RTL.

The folder ACL-Tester-Design-Single-Clock-Verilog contains a Xilinx Vivado project with RTL sources containing only Verilog-2001 modules. Plain HDL without a soft CPU or C code is authored to talk with board components, an accelerometer peripheral, a 16x2 character LCD peripheral and a two-digit Seven Segment Display. The project is named “Single Clock” as clock enable pulses are used instead of clock dividers as much as possible throughout the design.

In addition to the project’s Verilog RTL and Xilinx Vivado project, a VHDL-2008 test-bench was added. This test-bench provides a beginning of an OS-VVM verification environment. It starts out as identical to the VHDL-2008 test-bench added to the VHDL-Only RTL project, as mentioned in previous post

VHDL Verification of fpga-serial-acl-tester-1 with open source tools

Currently only one test is implemented, providing both manual and automated checking of the Measurement Mode operation of the Verilog DUT (Device Under Test). The folder Work_Dir_RivPro contains a collection of scripts, executed by running the asim-run-mixed.do script within the Riviera-PRO TCL command-line. It compiles the Verilog RTL, the VHDL test-bench, and runs the simulation from start to finish. Note that this script executes the behavioral simulation verification of the Verilog design with a VHDL test-bench; and that the simulation is independent of the Vivado 2020.2 project. (It performs a pre-synthesis simulation.) Note that this mixed-language simulation is a capability that the open source Verilog and VHDL simulators are not currently capable of performing. Also note that the Xilinx Vivado 2020.2 tool is not capable to the same degree, due to not supporting several key VHDL-2008 languge features.

The test-bench was authored to instantiate the FPGA design, and also instantiate test-bench components to emulate the peripherals that the FPGA is designed to interact with. These are:

Board User Interface
- 4 Basic LEDs
- 4 RGB LEDs
- 4 Switches
- 4 Buttons
Board UART
- Monitoring and Scoreboarding of FPGA UART output as ASCII Text
Clock and Reset Generator
Pmod SSD (7SD)
- Monitoring of the two digits displayed multiplexed on the Pmod SSD
Pmod CLS
- Monitoring and Scoreboarding of received SPI data as ASCII Text with ANSI control sequences
Pmod ACL2
- A model that emulates the ADXL362 accelerometer’s capability of Measurement Mode, where measurements are output via SPI at a data ready frequency

Note that the OS-VVM test-bench can be configured to select different architectures of test-bench entities, exactly as described in the previous post

VHDL Verification of fpga-serial-acl-tester-1 with open source tools

As described in the prior post, the execution of the test-bench happens by compiling all project sources, and then selecting a VHDL Configuration as target to elaborate and simulate. In this way, an OS-VVM test-bench can be authored to verify an FPGA design whose RTL is one of: VHDL-only, Verilog-only, mixed VHDL and Verilog. (Note that the author is omitting mention of SystemVerilog RTL and other HDL languages, which can also be part of the RTL code base.)

Of final note: to my knowledge, it is proper that the VHDL Configuration not specifiy architecture, port map, or generic map, of any RTL in hierarchy that is of a language other than VHDL. Thus, the VHDL Configuration source would be:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library osvvm;
context osvvm.OsvvmContext;

library work;
use work.all;

configuration test_default_fpga_regression of fpga_serial_acl_tester_testharness is
  for simulation
    for u_fpga_serial_acl_tester_testbench : fpga_serial_acl_tester_testbench
      use entity work.fpga_serial_acl_tester_testbench(simulation)
      generic map(
        -- specify simulation duration for this test
        parm_simulation_duration => 750 ms,

        -- specify log file name for this test
        parm_log_file_name => "log_test_default_fpga_regression.txt"
      );

      for simulation
      	-- No portion of the Verilog RTL of the DUT is configured as the
      	-- RTL language is not VHDL.
        --for uut_fpga_serial_acl_tester : fpga_serial_acl_tester
        --  use entity work.fpga_serial_acl_tester(rtl);
        --end for;

        for u_tbc_clock_gen : tbc_clock_gen
          -- specify the component architecture to generate
          -- the clock and reset
          use entity work.tbc_clock_gen(simulation_default);
        end for;

        for u_tbc_board_ui : tbc_board_ui
          -- specify the component architecture to emulate/
          -- monitor/check the user interface board components
          use entity work.tbc_board_ui(simulation_default);
        end for;

        for u_tbc_pmod_acl2 : tbc_pmod_acl2
          -- specify the component architecture to emulate/
          -- monitor/check the accelerometer peripheral
          use entity work.tbc_pmod_acl2(simulation_default);
        end for;

        for u_tbc_pmod_cls : tbc_pmod_cls
          -- specify the component architecture to emulate/
          -- monitor/check the 16x2 LCD peripheral
          use entity work.tbc_pmod_cls(simulation_default);
        end for;

        for u_tbc_board_uart : tbc_board_uart
          -- specify the component architecture to emulate/
          -- monitor/check the UART terminal
          use entity work.tbc_board_uart(simulation_default);
        end for;

        for u_tbc_pmod_7sd : tbc_pmod_7sd
          -- specify the component architecture to emulate/
          -- monitor/check the 2-digit 7-segment display
          use entity work.tbc_pmod_7sd(simulation_default);
        end for;
      end for;
    end for;
  end for;
end configuration test_default_fpga_regression;

Of note, the execution of the simulation with a Verilog RTL FPGA top requires a compilation of work.glbl and specifying that unit name with the VHDL configuration name, on the TCL command-line, when invoking the elaborate-simulate command asim.

The TCL simulation script looks like this.

source ./asim-compile-osvvm.do
source ./asim-compile-work-mixed.do

asim +access -dbg -L unisims_ver -L unimacro_ver work.test_default_fpga_regression work.glbl
run -all

Refer to the scripts asim-compile-osvvm.do and asim-compile-work-mixed.do for futher examples of compiling Verilog and VHDL into the same work library, while using Xilinx UNIMACRO macros in the RTL for hard FPGA resources such as MMCM, and block-RAM FIFOs.