OS-VVM VHDL project simulations with GHDL 3.0
OS-VVM VHDL project simulations with GHDL 3.0
Instructions on installing GHDL 3.0 from source on Ubuntu 22.04.3 LTS and simulating an example OS-VVM test-bench to verify a VHDL RTL project.
by Timothy Stotts
Understanding GHDL 3.0 installation options
When installing GHDL from source code, there are 3 backends to choose from:
- mcode: recommended by the GHDL author to save compilation time on small projects
- GCC: requires download of the sources of the GNU Compiler Collection
- LLVM: requires a simple install of LLVM, CLang, GNAT, and a newer C++ library includes
With this example, the GHDL 3.0 program will be compiled with the LLVM backend. The Xilinx Vivado 2021.2 UNISIM and UNIMACRO libraries will be compiled with GHDL. And then, an example VHDL project plus OS-VVM libraries will be compiled and simulated.
Note that the mcode backend is not used in this example
as it has an overflow error simulation
halt whenever simulating the OS-VVM UART model. Some sparse mention on the internet
about this bug suggests that GHDL mcode operates best on x86 32-bit systems
instead of the modern amd64/x86_64 64-bit workstation processors.
LLVM is an easy alternative backend.
The workstation this example was performed on
For this example, it is helpful to use an Ubuntu Linux Workstation that is sufficiently fast for single-thread execution. Here’s the system I ran this example on.
~$ neofetch
`.:/ossyyyysso/:. timothystotts@d1study
.:oyyyyyyyyyyyyyyyyyyo:` ---------------------
-oyyyyyyyodMMyyyyyyyysyyyyo- OS: Kubuntu 22.04.3 LTS x86_64
-syyyyyyyyyydMMyoyyyydmMMyyyyys- Host: Dev One Notebook PC
oyyysdMysyyyydMMMMMMMMMMMMMyyyyyyyo Kernel: 6.2.0-37-generic
`oyyyydMMMMysyysoooooodMMMMyyyyyyyyyo` Uptime: 26 mins
oyyyyyydMMMMyyyyyyyyyyyysdMMysssssyyyo Packages: 2656 (dpkg), 20 (snap)
-yyyyyyyydMysyyyyyyyyyyyyyysdMMMMMysyyy- Shell: bash 5.1.16
oyyyysoodMyyyyyyyyyyyyyyyyyyydMMMMysyyyo Resolution: 1920x1080
yyysdMMMMMyyyyyyyyyyyyyyyyyyysosyyyyyyyy DE: Plasma 5.24.7
yyysdMMMMMyyyyyyyyyyyyyyyyyyyyyyyyyyyyyy WM: kwin
oyyyyysosdyyyyyyyyyyyyyyyyyyydMMMMysyyyo Theme: [Plasma], Breeze [GTK2/3]
-yyyyyyyydMysyyyyyyyyyyyyyysdMMMMMysyyy- Icons: [Plasma], breeze [GTK2/3]
oyyyyyydMMMysyyyyyyyyyyysdMMyoyyyoyyyo Terminal: konsole
`oyyyydMMMysyyyoooooodMMMMyoyyyyyyyyo CPU: AMD Ryzen 7 PRO 5850U with Radeon Graphics (16) @ 1.900GHz
oyyysyyoyyyysdMMMMMMMMMMMyyyyyyyyo GPU: AMD ATI 03:00.0 Cezanne
-syyyyyyyyydMMMysyyydMMMysyyyys- Memory: 1793MiB / 63614MiB
-oyyyyyyydMMyyyyyyysosyyyyo-
./oyyyyyyyyyyyyyyyyyyo/.
`.:/oosyyyysso/:.`
Note that this budget HP Linux workstation is capable of executing a program at over 4.0 GHz CPU core speed, and it has a decent amount of L2 and L3 cache. That is helpful for quicker execution of the test-bench simulation. Also note that the workstation is running an Ubuntu 22.04 install which was later switched to the full Kubuntu 22.04 install without removing the original Ubuntu 22.04. That might make a difference in the default installed libraries already on the system. As such, I may not have mentioned every GHDL prerequisite due to tools or libraries already installed. [Edit 2023-11-25.] Consider installing all prerequisites for Vitis and Vivado 2021.2, as there will be overlap. Details can be found at the post Installing Xilinx Vitis and Vivado 2021.2 on Ubuntu Desktop 22.04.
Compiling GHDL 3.0 with the LLVM backend
Installing prerequisite system tools and libraries [edited 2023-11-25]
GHDL 3.0 requires the following non-default tools and libraries to be installed on Ubuntu 22.04.
- GCC GNAT - the ADA language compiler
- LLVM - the Low Level Virtual Machine compilation tool library
- CLang - a specific alternative C and C++ compiler
- Std C++ 12 headers - a set of C++ headers that are newer than the default version 11
- Headers for ZLib - compilation headers for the zlib1g ZLib library.
Here is how to install the default version of these with documentation easily on Ubuntu 22.04:
~$ sudo apt install gnat clang llvm-dev libstdc++-12-dev zlib1g-dev
~$ sudo apt install gnat-10-doc clang-14-doc llvm-14-doc libstdc++-12-doc
Note that the -doc packages are optional, but could prove useful for reading manual pages offline should the user have any questions regarding these tools, now, or in the future.
Download GHDL 3.0 from GitHub
GHDL can be downloaded as pre-compiled binaries or as source code. With this example, we will be installing from source.
Navigate with a web browser to the GHDL release page: GDHL Releases
Download from the source code link the file at tag v3.0.0.tar.gz . GHDL 3.0.0 source
Extract this program’s source code to a temporary folder:
~$ mkdir -p ~/tmp/
~$ cd ~/tmp/
~/tmp$ tar -x -z -f ~/Downloads/ghdl-3.0.0.tar.gz
Install GHDL 3.0 with the LLVM backend
To compile and install GHDL with LLVM backend, it is recommended to install to the
prefix /usr/local/ instead of /usr/ to prevent conflict with any apt packages.
This also compiles with LLVM 14 instead of mcode. Here’s how:
~/tmp$ cd ~/tmp/ghdl-3.0.0/
~/tmp/ghdl-3.0.0
$ ./configure --prefix=/usr/local --with-llvm-config=$(which llvm-config-14)
$ make
$ sudo make install
$ cd ~/
~$ ghdl --version
GHDL 3.0.0 (tarball) [Dunoon edition]
Compiled with GNAT Version: 10.5.0
llvm 14.0.0 code generator
Written by Tristan Gingold.
Copyright (C) 2003 - 2023 Tristan Gingold.
GHDL is free software, covered by the GNU General Public License. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
Downloading an example OS-VVM-based VHDL project and simulating
This author has previously created a GitHub project called fpga-serial-acl-tester-3. (This project was updated recently to again execute with GHDL, same as worked before adding Arty S7-25 board support. The changes were only entity and file names. The simulation runs with Arty A7-100 as the target; but it would be possible to enhance the test-bench to target either board.)
FPGA Serial ACL Tester Version 3 project and source code
To clone this project with GIT with your GitHub account into a local workarea on an Ubuntu workstation, and begin setup of the example, do this:
~$ git clone --recursive \
git@github.com:timothystotts/fpga-serial-acl-tester-3.git \
fpga-serial-acl-tester-3-ghdl3
~$ cd ./fpga-serial-acl-tester-3-ghdl3/ACL-Tester-Design-VHDL/Work_Dir_GHDL/
Note that the OS-VVM check-out is two commits ahead of release 2021.10, as this is the
OS-VVM version that was cloned at the time of the release of this project.
Also note that it is necessary to compile the Xilinx UNISIM and UNIMACRO sources as
they are used in the VHDL RTL source. This assumes that Xilinx Vivado 2021.2 application
is installed on the Linux workstation under path /opt/Xilinx/Vivado/2021.2 . If this is
the case, here’s how to automatically compile and setup the UNISIM and UNIMACRO sources for GHDL:
~/fpga-serial-acl-tester-3-ghdl3/ACL-Tester-Design-VHDL/Work_Dir_GHDL
$ /usr/local/lib/ghdl/vendors/compile-xilinx-vivado.sh \
--unisim --unimacro --vhdl2008
$ ln -s xilinx-vivado/unisim ./
$ ln -s xilinx-vivado/unimacro ./
$ ./ghdl-run.sh run
Example output of the run script, not including any compile-time and execution-time warning messages:
./ghdl-run.sh run
ghdl -a --std=08 --work=osvvm -O2 ../OSVVM/OsvvmLibraries/osvvm/ResolutionPkg.vhd
ghdl -a --std=08 --work=osvvm -O2 ../OSVVM/OsvvmLibraries/osvvm/NamePkg.vhd
ghdl -a --std=08 --work=osvvm -O2 ../OSVVM/OsvvmLibraries/osvvm/NameStorePkg.vhd
ghdl -a --std=08 --work=osvvm -O2 ../OSVVM/OsvvmLibraries/osvvm/OsvvmGlobalPkg.vhd
ghdl -a --std=08 --work=osvvm -O2 ../OSVVM/OsvvmLibraries/osvvm/VendorCovApiPkg.vhd
ghdl -a --std=08 --work=osvvm -O2 ../OSVVM/OsvvmLibraries/osvvm/TranscriptPkg.vhd
ghdl -a --std=08 --work=osvvm -O2 ../OSVVM/OsvvmLibraries/osvvm/TextUtilPkg.vhd
ghdl -a --std=08 --work=osvvm -O2 ../OSVVM/OsvvmLibraries/osvvm/AlertLogPkg.vhd
ghdl -a --std=08 --work=osvvm -O2 ../OSVVM/OsvvmLibraries/osvvm/MessageListPkg.vhd
ghdl -a --std=08 --work=osvvm -O2 ../OSVVM/OsvvmLibraries/osvvm/SortListPkg_int.vhd
ghdl -a --std=08 --work=osvvm -O2 ../OSVVM/OsvvmLibraries/osvvm/RandomBasePkg.vhd
ghdl -a --std=08 --work=osvvm -O2 ../OSVVM/OsvvmLibraries/osvvm/RandomPkg.vhd
ghdl -a --std=08 --work=osvvm -O2 ../OSVVM/OsvvmLibraries/osvvm/RandomProcedurePkg.vhd
ghdl -a --std=08 --work=osvvm -O2 ../OSVVM/OsvvmLibraries/osvvm/CoveragePkg.vhd
ghdl -a --std=08 --work=osvvm -O2 ../OSVVM/OsvvmLibraries/osvvm/MemoryPkg.vhd
ghdl -a --std=08 --work=osvvm -O2 ../OSVVM/OsvvmLibraries/osvvm/ScoreboardGenericPkg.vhd
ghdl -a --std=08 --work=osvvm -O2 ../OSVVM/OsvvmLibraries/osvvm/ScoreboardPkg_slv.vhd
ghdl -a --std=08 --work=osvvm -O2 ../OSVVM/OsvvmLibraries/osvvm/ScoreboardPkg_int.vhd
ghdl -a --std=08 --work=osvvm -O2 ../OSVVM/OsvvmLibraries/osvvm/ResizePkg.vhd
ghdl -a --std=08 --work=osvvm -O2 ../OSVVM/OsvvmLibraries/osvvm/TbUtilPkg.vhd
ghdl -a --std=08 --work=osvvm -O2 ../OSVVM/OsvvmLibraries/osvvm/ReportPkg.vhd
ghdl -a --std=08 --work=osvvm -O2 ../OSVVM/OsvvmLibraries/osvvm/OsvvmContext.vhd
ghdl -a --std=08 --work=OSVVM_Common -O2 ../OSVVM/OsvvmLibraries/Common/src/StreamTransactionPkg.vhd
ghdl -a --std=08 --work=OSVVM_Common -O2 ../OSVVM/OsvvmLibraries/Common/src/AddressBusTransactionPkg.vhd
ghdl -a --std=08 --work=OSVVM_Common -O2 ../OSVVM/OsvvmLibraries/Common/src/AddressBusResponderTransactionPkg.vhd
ghdl -a --std=08 --work=OSVVM_Common -O2 ../OSVVM/OsvvmLibraries/Common/src/AddressBusVersionCompatibilityPkg.vhd
ghdl -a --std=08 --work=OSVVM_Common -O2 ../OSVVM/OsvvmLibraries/Common/src/ModelParametersPkg.vhd
ghdl -a --std=08 --work=OSVVM_Common -O2 ../OSVVM/OsvvmLibraries/Common/src/FifoFillPkg_slv.vhd
ghdl -a --std=08 --work=OSVVM_Common -O2 ../OSVVM/OsvvmLibraries/Common/src/InterruptHandler.vhd
ghdl -a --std=08 --work=OSVVM_Common -O2 ../OSVVM/OsvvmLibraries/Common/src/InterruptHandlerComponentPkg.vhd
ghdl -a --std=08 --work=OSVVM_Common -O2 ../OSVVM/OsvvmLibraries/Common/src/OsvvmCommonContext.vhd
ghdl -a --std=08 --work=osvvm_uart -O2 ../OSVVM/OsvvmLibraries/UART/src/UartTbPkg.vhd
ghdl -a --std=08 --work=osvvm_uart -O2 ../OSVVM/OsvvmLibraries/UART/src/ScoreboardPkg_Uart.vhd
ghdl -a --std=08 --work=osvvm_uart -O2 ../OSVVM/OsvvmLibraries/UART/src/UartTxComponentPkg.vhd
ghdl -a --std=08 --work=osvvm_uart -O2 ../OSVVM/OsvvmLibraries/UART/src/UartRxComponentPkg.vhd
ghdl -a --std=08 --work=osvvm_uart -O2 ../OSVVM/OsvvmLibraries/UART/src/UartContext.vhd
ghdl -a --std=08 --work=osvvm_uart -O2 ../OSVVM/OsvvmLibraries/UART/src/UartTx.vhd
ghdl -a --std=08 --work=osvvm_uart -O2 ../OSVVM/OsvvmLibraries/UART/src/UartRx.vhd
ghdl -a --std=08 --work=work -O2 ../RTL/clock_divider.vhdl
ghdl -a --std=08 --work=work -O2 ../RTL/clock_enable_divider.vhdl
ghdl -a --std=08 --work=work -O2 ../RTL/arty_reset_synchronizer.vhdl
ghdl -a --std=08 --work=work -O2 ../RTL/ext_interrupt_debouncer.vhdl
ghdl -a --std=08 --work=work -O2 ../RTL/lcd_text_functions_pkg.vhdl
ghdl -a --std=08 --work=work -O2 ../RTL/multi_input_debounce.vhdl
ghdl -a --std=08 --work=work -O2 ../RTL/one_shot_fsm.vhdl
ghdl -a --std=08 --work=work -O2 ../RTL/pulse_stretcher_synch.vhdl
ghdl -a --std=08 --work=work -O2 ../RTL/ssd_display.vhdl
ghdl -a --std=08 --work=work -O2 ../RTL/thresh_presets_selector.vhdl
ghdl -a --std=08 --work=work -O2 ../RTL/thresh_presets_pkg.vhdl
ghdl -a --std=08 --work=work -O2 ../RTL/acl_tester_fsm.vhdl
ghdl -a --std=08 --work=work -O2 ../RTL/adxl362_readings_to_ascii.vhdl
ghdl -a --std=08 --work=work -O2 ../RTL/lcd_text_feed.vhdl
ghdl -a --std=08 --work=work -O2 ../RTL/led_pwm_driver.vhdl
ghdl -a --std=08 --work=work -O2 ../RTL/led_palette_pulser.vhdl
ghdl -a --std=08 --work=work -O2 ../RTL/pmod_stand_spi_solo_pkg.vhdl
ghdl -a --std=08 --work=work -O2 ../RTL/pmod_generic_spi_solo.vhdl
ghdl -a --std=08 --work=work -O2 ../RTL/pmod_acl2_stand_spi_solo.vhdl
ghdl -a --std=08 --work=work -O2 ../RTL/pmod_cls_stand_spi_solo.vhdl
ghdl -a --std=08 --work=work -O2 ../RTL/pmod_acl2_custom_driver.vhdl
ghdl -a --std=08 --work=work -O2 ../RTL/pmod_cls_custom_driver.vhdl
ghdl -a --std=08 --work=work -O2 ../RTL/uart_tx_feed.vhdl
ghdl -a --std=08 --work=work -O2 ../RTL/uart_tx_only.vhdl
ghdl -a --std=08 --work=work -O2 ../RTL/fpga_serial_acl_tester_a7100.vhdl
ghdl -a --std=08 --work=work -O2 ../Testbench/acl_testbench_pkg.vhdl
ghdl -a --std=08 --work=work -O2 ../Testbench/clock_gen.vhdl
ghdl -a --std=08 --work=work -O2 ../Testbench/board_ui.vhdl
ghdl -a --std=08 --work=work -O2 ../Testbench/pmod_acl2.vhdl
ghdl -a --std=08 --work=work -O2 ../Testbench/board_uart.vhdl
ghdl -a --std=08 --work=work -O2 ../Testbench/pmod_cls.vhdl
ghdl -a --std=08 --work=work -O2 ../Testbench/pmod_7sd.vhdl
ghdl -a --std=08 --work=work -O2 ../Testbench/fpga_serial_acl_tester_testbench.vhdl
ghdl -a --std=08 --work=work -O2 ../Testbench/fpga_serial_acl_tester_testharness.vhdl
ghdl -a --std=08 --work=work -O2 ../Testbench/test_default_fpga_regression.vhdl
ghdl -e --std=08 -fsynopsys -frelaxed -O2 test_default_fpga_regression
ghdl -r --std=08 -fsynopsys -frelaxed test_default_fpga_regression ---vcd=test.vcd ---write-wave-opt=test.opt --stop-time=1us
FPGA_SERIAL_ACL_TESTER_TESTBENCH starting simulation.
Logging enabled for ALWAYS, INFO, DEBUG.
%% Log ALWAYS in u_tbc_clock_gen, Starting system clock emulation with period 10000000 fs. at 1 ns
%% Log ALWAYS in u_tbc_board_ui, Starting board user interface emulation, 4 buttons, 4 switches, 4 RGB LEDs, 4 Basic LEDs. at 1 ns
%% Log ALWAYS in u_tbc_pmod_acl2, Starting Pmod ACL2 emulation with SPI mode 0 bus, two interrupt lines, internal clock of 8.0 MHz. at 1 ns
%% Log ALWAYS in u_tbc_pmod_cls, Starting Pmod CLS emulation with SPI mode 0 bus. at 1 ns
%% Log ALWAYS in u_tbc_board_uart, Starting Board UART emulation at baud 115200. at 1 ns
%% Log ALWAYS in u_tbc_pmod_7sd, Starting monitoring emulation of Pmod SSD (7SD). at 1 ns
%% Log ALWAYS in u_tbc_pmod_cls, Entering Pmod CLS emulation with SPI mode 0 bus. at 2 ns
%% Log ALWAYS in u_tbc_pmod_acl2, Entering Pmod ACL2 emulation of interrupt lines. at 2 ns
%% Log ALWAYS in u_tbc_pmod_acl2, Entering Pmod ACL2 emulation of Data Ready filter control. at 2 ns
%% Log ALWAYS in u_tbc_pmod_acl2, Updating Pmod ACL2 emulation of Data Ready filter control executing with period 2500000000000 fs . at 2 ns
%% Log ALWAYS in u_tbc_pmod_acl2, Entering Pmod ACL2 emulation with SPI mode 0 bus. at 2 ns
%% Log ALWAYS in u_tbc_board_ui, Entering emulation of switches 0,1,2,3 . at 2 ns
%% Log INFO in u_tbc_board_ui, BOARD UI switches 0,1,2,3 unselected at startup. at 2 ns
%% Log ALWAYS in u_tbc_board_ui, Entering emulation of buttons 0,1,2,3 . at 2 ns
%% Log INFO in u_tbc_board_ui, BOARD UI buttons 0,1,2,3 released at startup. at 2 ns
%% Log ALWAYS in u_tbc_clock_gen, Delaying external reset running with delay 1000000000 fs. at 2 ns
%% Log ALWAYS in u_tbc_clock_gen, Entering external clock running with period 10000000 fs and 50% duty cycle. at 2 ns
./test_default_fpga_regression:info: simulation stopped by --stop-time @1us
ghdl -r --std=08 -fsynopsys -frelaxed test_default_fpga_regression
FPGA_SERIAL_ACL_TESTER_TESTBENCH starting simulation.
Logging enabled for ALWAYS, INFO, DEBUG.
%% Log ALWAYS in u_tbc_clock_gen, Starting system clock emulation with period 10000000 fs. at 1 ns
%% Log ALWAYS in u_tbc_board_ui, Starting board user interface emulation, 4 buttons, 4 switches, 4 RGB LEDs, 4 Basic LEDs. at 1 ns
%% Log ALWAYS in u_tbc_pmod_acl2, Starting Pmod ACL2 emulation with SPI mode 0 bus, two interrupt lines, internal clock of 8.0 MHz. at 1 ns
%% Log ALWAYS in u_tbc_pmod_cls, Starting Pmod CLS emulation with SPI mode 0 bus. at 1 ns
%% Log ALWAYS in u_tbc_board_uart, Starting Board UART emulation at baud 115200. at 1 ns
%% Log ALWAYS in u_tbc_pmod_7sd, Starting monitoring emulation of Pmod SSD (7SD). at 1 ns
%% Log ALWAYS in u_tbc_pmod_cls, Entering Pmod CLS emulation with SPI mode 0 bus. at 2 ns
%% Log ALWAYS in u_tbc_pmod_acl2, Entering Pmod ACL2 emulation of interrupt lines. at 2 ns
%% Log ALWAYS in u_tbc_pmod_acl2, Entering Pmod ACL2 emulation of Data Ready filter control. at 2 ns
%% Log ALWAYS in u_tbc_pmod_acl2, Updating Pmod ACL2 emulation of Data Ready filter control executing with period 2500000000000 fs . at 2 ns
%% Log ALWAYS in u_tbc_pmod_acl2, Entering Pmod ACL2 emulation with SPI mode 0 bus. at 2 ns
%% Log ALWAYS in u_tbc_board_ui, Entering emulation of switches 0,1,2,3 . at 2 ns
%% Log INFO in u_tbc_board_ui, BOARD UI switches 0,1,2,3 unselected at startup. at 2 ns
%% Log ALWAYS in u_tbc_board_ui, Entering emulation of buttons 0,1,2,3 . at 2 ns
%% Log INFO in u_tbc_board_ui, BOARD UI buttons 0,1,2,3 released at startup. at 2 ns
%% Log ALWAYS in u_tbc_clock_gen, Delaying external reset running with delay 1000000000 fs. at 2 ns
%% Log ALWAYS in u_tbc_clock_gen, Entering external clock running with period 10000000 fs and 50% duty cycle. at 2 ns
%% Log ALWAYS in u_tbc_clock_gen, Entering external reset running low with period 1000000000 fs. at 1002 ns
%% Log INFO in u_tbc_board_ui, BASIC LED PWM 3 lasted for: L:1010000000 fs at 1022 ns
%% Log INFO in u_tbc_board_ui, BASIC LED PWM 3 changed to: L:0 at 1022 ns
%% Log INFO in u_tbc_board_ui, BASIC LED PWM 2 lasted for: L:1010000000 fs at 1022 ns
%% Log INFO in u_tbc_board_ui, BASIC LED PWM 2 changed to: L:0 at 1022 ns
%% Log INFO in u_tbc_board_ui, BASIC LED PWM 1 lasted for: L:1010000000 fs at 1022 ns
%% Log INFO in u_tbc_board_ui, BASIC LED PWM 1 changed to: L:0 at 1022 ns
%% Log INFO in u_tbc_board_ui, BASIC LED PWM 0 lasted for: L:1010000000 fs at 1022 ns
%% Log INFO in u_tbc_board_ui, BASIC LED PWM 0 changed to: L:0 at 1022 ns
%% Log INFO in u_tbc_board_ui, RGB LED PWM 0 lasted for: R:1010000000 fs G:1010000000 fs B:1010000000 fs at 1022 ns
%% Log INFO in u_tbc_board_ui, RGB LED PWM 0 changed to: R:0 G:0 B:0 at 1022 ns
%% Log INFO in u_tbc_board_ui, RGB LED PWM 1 lasted for: R:1010000000 fs G:1010000000 fs B:1010000000 fs at 1022 ns
%% Log INFO in u_tbc_board_ui, RGB LED PWM 1 changed to: R:0 G:0 B:0 at 1022 ns
%% Log INFO in u_tbc_board_ui, RGB LED PWM 2 lasted for: R:1010000000 fs G:1010000000 fs B:1010000000 fs at 1022 ns
%% Log INFO in u_tbc_board_ui, RGB LED PWM 2 changed to: R:0 G:0 B:0 at 1022 ns
%% Log INFO in u_tbc_board_ui, RGB LED PWM 3 lasted for: R:1010000000 fs G:1010000000 fs B:1010000000 fs at 1022 ns
%% Log INFO in u_tbc_board_ui, RGB LED PWM 3 changed to: R:0 G:0 B:0 at 1022 ns
%% Log INFO in u_tbc_pmod_7sd, 7SD Digit 0 is turned OFF: 0000000 at 6162 ns
%% Log INFO in u_tbc_board_ui, BOARD UI button 0 depressed. at 2003012 ns
%% Log INFO in u_tbc_pmod_cls, PMOD CLS received control line of 4.0 bytes: 1B5B306A decoded: \x[0j at 2080862 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 58, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 1 at 2103501.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 3A, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 2 at 2190301.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 5F, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 3 at 2277101.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 5F, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 4 at 2363901.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 5F, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 5 at 2450701.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 5F, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 6 at 2537501.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 20, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 7 at 2624301.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 20, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 8 at 2711101.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 59, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 9 at 2797901.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 3A, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 10 at 2884701.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 5F, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 11 at 2971501.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 5F, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 12 at 3058301.25 ns
%% Log INFO in u_tbc_pmod_cls, PMOD CLS received control line of 7.0 bytes: 1B5B303B303048 decoded: \x[0;00H at 3120862 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 5F, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 13 at 3145101.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 5F, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 14 at 3231901.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 20, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 15 at 3318701.25 ns
%% Log INFO in u_tbc_pmod_cls, PMOD CLS received text line of 1.6e1 bytes: 585F5F5F5F5F5F20595F5F5F5F5F5F20 decoded: X______ Y______ at 3359262 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 20, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 16 at 3405501.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 5A, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 17 at 3492301.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 3A, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 18 at 3579101.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 5F, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 19 at 3665901.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 5F, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 20 at 3752701.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 5F, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 21 at 3839501.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 5F, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 22 at 3926301.25 ns
%% Log INFO in u_tbc_board_ui, BOARD UI button 0 released. at 4003012 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 20, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 23 at 4013101.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 20, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 24 at 4099901.25 ns
%% Log INFO in u_tbc_pmod_cls, PMOD CLS received control line of 7.0 bytes: 1B5B313B303048 decoded: \x[1;00H at 4122462 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 54, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 25 at 4186701.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 3A, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 26 at 4273501.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 5F, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 27 at 4360301.25 ns
%% Log INFO in u_tbc_pmod_cls, PMOD CLS received text line of 1.6e1 bytes: 5A5F5F5F5F5F5F20545F5F5F5F5F2020 decoded: Z______ T_____ at 4360862 ns
%% Alert WARNING in u_tbc_pmod_cls, PMOD CLS text lines not tested with ScoreBoard history. at 4360862 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 5F, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 28 at 4447101.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 5F, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 29 at 4533901.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 5F, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 30 at 4620701.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 20, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 31 at 4707501.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 20, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 32 at 4794301.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 0D, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 33 at 4881101.25 ns
%% Log INFO in u_osvvm_uart_rx, Received: Data = 0A, Parity Error: 0, Stop Error: 0, Break Error: 0. Operation # 34 at 4967901.25 ns
%% Log INFO in u_tbc_board_uart, UART Received from FPGA the ASCII line: X:____ Y:____ Z:____ T:____ at 4967901.25 ns
%% Alert WARNING in u_tbc_board_uart, BOARD UART text line not tested with ScoreBoard history. at 4967901.25 ns
%% Log INFO in u_tbc_board_ui, BOARD UI switch 0 selected. at 5003012 ns
Conclusions
Hopefully this post has been helpful for understanding the possibilities of simulating your own VHDL-2008 project with GHDL. The program GHDL is mature and open-source, and can be useful for VHDL projects at school, hobby, or employment.
Also, I hope that the fpga-serial-acl-tester-3 project is useful for not only RTL design, but for ideas for how to structure the start of a VHDL-2008 test-bench.
Cheers.